AT76C001 cbic programmable fir filter AT76C001 features 4 multiplier-accumulators 40 bits accuracy 16 bit data and coefficients 4-tap filter with 27 mhz sample rate programmable to give up to 256 taps with sampling reducing proportionally to 421,875 khz programmable rounding and truncation to 16 bit 8 bit standard microprocessor interface 64-pin pqfp, 68-pin pga68 or 68-pin lcc68 packaging description the AT76C001 programmable finite impulse response (fir) filter implements a 4th order fir cell built around 4 multiplier-accumulators. it contains a dual-port ram and a ram which are used to implement fir filters of up to 256 taps. high or- der filters are achieved by multiplexing the 4th order cell and accumulating the inter- mediate results up to 40 bits, so that there is no loss of accuracy. the maximum frequency of the AT76C001 is 27 mhz. for 4-tap fir filter, the in- coming sample rate can be as high as 27 mhz. for higher order fir filters, the sample rate can be as high as the circuit frequency divided by the 4th order cell mul- tiplexing factor. a programmable normalization block allows the choice of the 16 significant bits from the 40 bit internal result which can be previously rounded by adding 0.5 lsb accord- ing to the 16 significant bit locations. the AT76C001 has a microprocessor inter- face which can be configured to be intel or motorola compatible. applications digital filters (video, audio, etc.) correlation image processing
name pin number type function qfp64 packaging lcc68 packaging pga68 packaging in<15:0> 34-40, 42, 44-51 27-33, 35, 37-44 k10-11, j10-11, h10- 11, g10, f10, e10-11, d10-11, c10-11, b11-10 i input sample div 33 26 l10 i input sample valid. active low rst_x1 32 24 k9 i force input sample to 0. useful for interpolation implementation out<15:0> 18-12, 10, 8-1 9-3, 1, 67-60 k1, j1-2, h1-2, g1-2, f2, e2, d1-2, c1-2, b1- 2, a2 o output filtered sample dov 19 10 k2 o output filtered sample valid. active low data<7:0> 21-24, 26, 28-30 13-16, 18, 20-22 l3, k4, l4, k5-7, l7, k8 i/o microprocessor interface data bus. used for accessing internal registers and to write the coefficients of the filter cs 52 46 b9 i chip select. active low ds/wr 53 47 a9 i microprocessor interface data strobe (motorola mode) or write signal (intel mode). active low rdwr/rd 54 48 b8 i microprocessor interface read/write signal (motorola mode) or read signal (intel mode). active low add<1:0> 63-64 57-58 a4, b3 i microprocessor interface address bus reset 31 23 l8 i circuit master reset. active low clock 56 50 b7 i circuit clock (27 mhz max) clock_bist 61 55 a5 i for internal use. connect to ground test_bist 20 12 k3 i for internal use. connect to ground vcc 11, 27, 43, 58, 60, 62 2, 19, 36, 52, 54, 56 b4-6, f1, f11, l6 power supply (+5v) gnd 9, 25, 41, 55, 57, 59 17, 34, 49, 51, 53 a6-8, e1, g11, l5 ground nc 11, 25, 45, 59 a3, a10, l2, l9 no connection pin description 52 53 54 55 56 57 58 59 60 61 62 63 64 32 31 30 29 28 27 26 25 24 23 22 21 20 12345678910111213141516171819 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 cs ds/wr rdwr/rd gnd clock gnd vcc gnd vcc clock_bist(0) vcc add1 add 0 rst-xi reset data0 data1 data2 vcc data3 gnd data4 data5 data6 data7 test_ bist (0) in0 in1 in2 in3 in4 in5 in6 in7 vcc in8 gnd in9 in10 in11 in12 in13 in14 in15 div out0 out1 out2 out3 out4 out5 out6 out7 gnd out8 vcc out9 out10 out11 out12 out13 out14 out15 dov AT76C001 qfp64 (0): connect to gnd plan view of AT76C001 in qfp64 package 2 AT76C001
28 29 30 31 32 33 34 35 36 37 38 39 40 8 7 6 5 4 3 2 1 68 67 66 65 64 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 in14 in13 in12 in11 in10 in9 gnd in8 vcc in7 in6 in5 in4 out14 out13 out12 out11 out10 out9 vcc out8 gnd out7 out6 out5 out4 nc* rst_xi reset data0 data1 data2 vcc data3 gnd data4 data5 data6 data7 test_bist(0) nc* dov nc* cs ds/wr rdwr/rd gnd clock gnd vcc gnd vcc clock_bist(0) vcc add1 add0 nc* out0 AT76C001 lcc68 (0): connect to gnd 26 div 44 in0 9 out15 27 in15 41 42 43 in3 in2 in1 63 62 61 out3 out2 out1 * no connection plan view of AT76C001 in lcc68 package l nc* data7 data5 gnd vcc data1 reset nc* out15 dov tc(0) data6 data4 data3 data2 data0 rst_xi out2 out1 add0 vcc vcc vcc clock rdwr/ rd cs out0 nc* add1 cb(0) gnd gnd gnd ds/wr div in15 in14 out14 out13 out12 out11 out10 out9 vcc out8 gnd out7 out6 out5 in13 in12 in11 in10 in9 gnd in8 vcc in7 in6 in5 in4 in0 in1 nc* out4 out3 in3 in2 1234567891011 k j h g f e d c b a AT76C001 pga68 (0): connect to gnd * no connection plan view of AT76C001 in pga68 package AT76C001 3
block diagram control unit coefficient ram sample ram fourth order fir cell register register register register normalisation multiplexer add<1:0> cs ds/wr rdwr/rd rst-xi div clock reset data <7:0> in<15:0> internal control signals dov out <15:0> fourth order fir cell mux mult register add register mux mult register add register mux mult register add register mux mult register add register from in<15:0> from data<7:0> from control unit to normalisation 4 AT76C001
functional description the AT76C001 has an architecture built around a 4-tap non-recursive filter cell. this allows a 4-tap filter to be im- plemented, e.g. y(n) = a(0)x(n) + a(1)x(n-1) + a(2)x(n-2) + a(3)x(n-3) where x = 16 bit incoming sample y = 16 bit filtered sample a = 16 bit coefficient this operating mode is called single mode. the AT76C001 can implement up to 256-tap filters by multiplexing the 4th order structure, using internal rams. nth order fir filters can be divided into p 4th-or- der fir sub-filters where p is the integer part of (n+3)/4. thus the complete filter is evaluated by accumulating the contributions of each elementary 4th order sub-filter: y(n) = y(n,0) + y(n,1) + ....... + y(n,p-1) where y(n,j) = a(4j)x(n-4j) + a(4j+1)x(n-4j-1) + a(4j+2)x(n-4j-2) + a(4j+3)x(n-4j-3) j = number of the sub-filter this operating mode is called sequential mode. if (n+3)/4 is greater than p, then some coefficients of the last sub-filter will be set to zero automatically by the circuit. in single mode, the incoming sample rate can be as high as the circuit frequency (27 mhz). a new incoming sam- ple is notified by a low level on div input signal and clocked by the rising edge of the circuit clock clock. if there is a low level set on div and then a low level is set on rst_xi input, then a zero sample is fed inter- nally into the circuit. for each new sample, a filtered sample is calculated. valid output filtered samples are notified by a low level on dov output signal. the timing diagram below illus- trates the single mode operation. in sequential mode, an n-tap filter is divided into p 4-tap filters. consequently, the incoming sample rate must be at least p times slower than the circuit rate. as in single mode, a new incoming sample is notified by a low level on div input signal and clocked by the rising edge clock. but here, div defines a temporal window where xin is valid and whose width must be at least one clock period and at most p-1 clock periods. the tim- ing diagrams below illustrate the case for an n-tap filter, where n is greater than 4 but less than 9, i.e., div must go to high level between two incoming signals. clock div rst_xi in out dov x0 x1 x2=0 x3=0 x4 x5 x6 x7=0 x8 y0 y1 y2 y3 y4 y5 y6 output valid input valid input forced to 0 timing diagram for single mode operation AT76C001 5
microprocessor interface the AT76C001 has an 8 bit configurable microprocessor interface comprising the following signals: data <7:0> 8 bit data bus adC <1:0> 2 bit address bus cs chip select ds/wr data strobe or write signal rdwr/rd read/write signal or read signal by setting bit 1 of the configuration interface (intel/ moto), it is possible to configure the microprocessor in- terface to be motorola or intel compatible. when cho- sen, the configuration must be locked by setting bit lock_cfg of the configuration register. this must be done first of all otherwise the circuit will not function prop- erly. configuration motorola mode intel mode intel/moto bit bit set to 0 bit set to 1 signals data<7:0> data<7:0> add<1:0> add<1:0> cs cs ds wr rd/wr rd internal registers the AT76C001 contains three internal registers accessi- ble in read and write via the microprocessor interface, as soon as it is configured and locked. they are: configuration register (cfgr) normalization and rounding register (norr) filter order register (filr) configuration register it is an 8 bit register mapped at address 1hex = 01bin bit 0 = start/stop activates/deactivates filtering bit 1 = intel/moto configures microprocessor interface to be intel or motorola. bit 2 = msb/lsb indicates if 16 bit coefficients are written with most significant byte or least significant byte ahead. bit 3 = lock_cfg locks the microprocessor interface configuration. bit 4 = sing/seq indicates the operating mode of the 4th order cell, i.e. single mode or sequential mode. bit 5 = buff_full indicates that the sample input buffer contains n samples when implementing an n-tap fir filter. (continued) clock div rst_xi in out dov x3 x4 = 0 y0 y1 y2 y4 x0 x1 x2 = 0 x5 = 0 y3 timing diagram for n-tap filter where 4AT76C001
internal registers (continued) (continued) bit 6 = last_sfilt indicates that the last sub-filter is accessed. bit 7 = end_incoeff indicates that the last coefficient of the last sub-filter is being accessed. bit no76543210 bit name end_in coeff last_s filt buff_ full sing/ seq cfg lock int/ moto msb/lsb start/ stop acc. mode rrrrr/wr/wr/wr/w reset value 10100010 normalization and rounding register the normalization and rounding register is a 5 bit regis- ter mapped at address 2h = 10b allows the selection of the 16 bit significant part of the internal 40 bit result; also defines the number of bits rounding value if rounding is desired. bit <3:0>= sel <3:0> selects the 16 bit part and defines the number of bits rounding value as illustrated in the following table: bit 3:0 out<15:0> rounding value (hex) 0000 res<31:16> 00 0000 8000 0001 res<32:17> 00 0001 0000 0010 res<33:18> 00 0002 0000 0011 res<34:19> 00 0004 0000 0100 res<35:20> 00 0008 0000 0101 res<36:21> 00 0010 0000 0110 res<37:22> 00 0020 0000 0111 res<38:23> 00 0040 0000 1xxx res<39:24> 00 0080 0000 bit 4 = rounden enables/disables rounding of the 40 bit result before normalization. bit no 4 3 2 1 0 bit name rounden sel3 sel2 sel1 sel0 access mode r/w r/w r/w r/w r/w reset value 00000 filter order register the filter order register is an 8 bit register mapped at ad- dress 3h=11b. it contains the number of the order of the filter to be implemented minus 1 . reset values bit no76543210 bit name filt7 filt6 filt5 filt4 filt3 filt2 filt1 filt0 acc. mode r/w r/w r/w r/w r/w r/w r/w r/w reset value 00000000 coefficient writing filter coefficients are stored internally by writing to ad- dress 0hex = 00bin. the bit msb/lsb of the configura- tion register indicates if the msb is sent before the lsb and vice versa. stored coefficients are not readable via the microprocessor interface. for an n-tap filter, 2xn writing is necessary. if n is not a multiple of 4, the re- maining coefficients of the last sub-filter are set automat- ically to zero. application examples a 4-tap fir filter in motorola mode example with coefficient msb ahead and rounding en- abled. y n = c 0 x n + c 1 x n-1 + c 2 x n-2 + c 3 x n-3 where y n is the output filtered sample, c is the coeffi- cient and x is the incoming samples. 1. firstly, unlock the microprocessor interface by writing a zero to bit 3 (this is normally performed by applying a master reset). 2. write 1100bin in the configuration register. this sets the configuration with bit 0 selecting stop mode, bit 1 selecting motorola mode, bit 2 selecting msb ahead, and bit 3 locks the configuration. 3. write the filter order-1 in the filt_ord register, i.e. 03hex. 4. write the 4 coefficients starting with the most signifi- cant byte of c 0 , then the lsb of c 0, etc . 5. write 00010bin in the norm register to enable round- ing, and to select range of bits, for example bits 33 to18 of the 40 bit internal result. 6. write 1101bin in the configuration register to start the filter. at each new incoming sample, xin, specified by a low level on div. the filtered sample xout is calculated and is notified by a low level on dov. the AT76C001 7
absolute maximum ratings (continued) (continued) filtered xout is output 4 clock cycles after the sam- pling of the corresponding xin input. a 130-tap fir filter in intel mode example with coefficient lsb ahead and rounding dis- abled. y n =c 0 x n + c 1 x n-1 + ....... + c 128 x n-12 + c 129 x n-129 1. firstly, unlock the microprocessor interface by writing a zero to bit 3 (this is normally performed by applying a master reset). 2. write 1010bin in the configuration register. this sets the configuration with bit 0 selecting stop mode, bit 1 selecting intel mode, bit 2 selecting lsb ahead, and bit 3 locks the configuration. 3. write the filter order-1 in the filt_ord register, i.e. 81hex 4. write the 130 coefficients beginning with the lsb of c 0 , then the msb of c 0 , etc. 5. write 11xxx in the norm register to disable rounding and to select bits 39 to 24 of the 40 bit internal result.. 6. write 1011bin in the configuration register to start the filter. at each new transition high to low on div input signal, a new sample is fed into the filter. the corre- sponding filtered sample is output 4+33 clock cycles later and specified by a low level on dov output sig- nal. here the incoming sample rate must at most be 33 times less than the circuit clock rate, where 33 rep- resents the number of times the 4th order cell is multi- plexed. electrical specifications absolute maximum ratings symbol parameter min max unit conditions v dd dc supply voltage -0.5 5.5 v v i dc input voltage -0.5 v dd + 0.5v v or see +-iik v o dc output voltage -0.5 v dd + 0.5v v or see +-iok +-iik dc input diode current 10 ma v i <-0.5v v i >v dd +0.5v +-iok dc output diode current 20 ma v o <-0.5v v o >v dd +0.5v i ol max continuous output current 10 ma industrial i oh - max continuous output current 10 ma industrial t sh time of outputs shorted 5sec t a temperature range -40 +85 c industrial t sg storage temperature -65 +150 c recommended operating conditions symbol parameter min typ max unit conditions v dd dc supply voltage 4.5 5.0 5.5 v v i dc input voltage 0 5.0 v dd v v o dc output voltage 0 5.0 v dd v t a temperature range -40 +85 c ind t r input rise time 15 ns 10%-90% cmos t f input fall time 15 ns 10%-90% cmos dc characteristics symbol parameter min max unit conditions i ih input leakage, no pullup -1.0 +1.0 ua v in = v dd = 5.5v i il input leakage, no pullup -1.0 +1.0 ua v in = 0 v dd =5.5v i oz high- impedance output current bi-directional pins -1.0 +1.0 ua v dd =5.5v v il low level input voltage 30% v dd v cmos inputs and bi-dir v ih high level input voltage 70% v dd v cmos inputs and bi-dir v ol low level output voltage 0.5 v i ol =5.0ma v oh high level output voltage v dd - 0.5 vi oh =5.0ma c in input capacitance 7pf application examples (continued) 8 AT76C001
ac characteristics code description min max units tcph clock period 37 ns tclh clock high 15 ns tcll clock low 15 ns twrp write/read period 37 ns twrh write/read high 15 ns twrl write/read low 15 ns tsis synchronous signals to rising clock setup 5ns tsih synchronous inputs to rising clock hold 5ns tsod synchronous outputs to rising clock delay 10 ns twrcld write/read to clock high 5 ns tacws asynchronous input setup 20 ns tacwh asynchronous inputs hold 5 ns taoe asynchronous output enable 12 ns taod asynchronous output disable 7 ns see the illustration below for the interpretations of these characteristics. clock rst_xi div xin dov xout ds motorola wr intel rd intel cs rd/wr motorola add data tclp tcll tclh tsis tsih tsod twrl twrcld twrh tacws twrp tacwh taoe taod data out data in ac characteristics for single mode operation AT76C001 9
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